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### VLSI DESIGN (QUESTION BANK)

DRONACHARYA GROUP OF INSTITUTIONS,GR. NOIDA

SESSION: 2013-14

SUBJECT: VLSI DESIGN (EEC-703)

1.     Describe about the different design methodologies used in VLSI Design.
2.     Discuss about the design flow of VLSI circuits in detail.
3.     With the help of different examples explain about the concepts of Regularity, Modularity and Locality.
4.     Draw the stick diagram of CMOS inverter.
5.     Derive the current voltage relationship of NMOS for different bias conditions.
6.     Describe about the different scaling techniques in detail.
7.     Explain about the small geometry effects.
8.     List and explain about the capacitances related to MOS under different bias conditions.
9.     Explain about Y-diagram and design hierarchy.
10.  With the help of diagrams explain about the Resistive load inverters.
11.  What is the advantage of active load inverter? Discuss the advantages and disadvantages of different active load inverters with suitable diagram.
12.  What is the cause of delay in CMOS inverter? Define the time delay parameters in CMOS.
13.  Explain with suitable diagram the working of a CMOS inverter and also give different voltage levels in all five regions.
14.  With the help of NMOS and PMOS characteristic curves explain the different regions of CMOS inverter, also explain why it exhibits a large gain in region3.
15.  Find the expression for time delay in CMOS inverter by approximate or average method and exact method.
16.  Derive the relationship between Current & Voltage for an NMOS enhancement transistor for cutoff, Linear and saturation. Explain in detail about the power consumption in CMOS inverter and also find the expression for it.
17.  Why threshold logic voltage of a CMOS inverter kept as 50% off supply voltage. Under what condition it can be maintained? Find the expression for it.
18.  What will happen if the current ratio of an NMOS and PMOS kept less than 1 and greater than 1?
19.  Give two different configurations of the BiCMOS inverter. How these configurations can provide a larger fan out?
20.  How the width of the uncertainty region can be kept small? Why a small uncertainty region results in a larger noise margin?
21.  Realize the CMOS full adder circuit with minimum number of transistors. What will happen if pull-up network is implemented by NMOS and pull down network is implemented by PMOS?
22.  Explain in detail about the transmission gate and also prove that the  effective impedance is independent of the output voltage
23.  With the help of suitable diagram explain the working of a two input depletion load NOR gate in transient and steady state, and also derive all the relevant equations for it.
24.  With the help of cascade inverter diagram explain the terms noise margin for logic ’’1’’ and ‘’0’’.
25.   Explain the term unstability related to CMOS inverter. Why it arrives and is there major consequence of it?
26.  Explain the structure and operation of the MOSFET under external biasing.
27.  What is MOSFET scaling? Explain the types of scaling. What are the advantages and disadvantages of scaling?
28.  Explain the process of fabrication of the NMOS transistor.
29.  Explain the differences between enhancement type and depletion type devices.

30.  Why drain current increases even the transistor is in saturation?